1. Field
The present invention relates to a nonvolatile semiconductor memory device having a stack gate structure including a floating gate electrode and a charge storage layer, and a method for manufacturing the nonvolatile semiconductor memory device.
2. Description of the Related Art
As an example of a typical nonvolatile semiconductor memory device, an NAND type flash memory having a floating gate electrode will be described.
The memory cell has a stack structure in which a tunneling insulating film and a floating gate electrode are formed on a semiconductor substrate, and furthermore, a control gate electrode is formed thereon through an inter-electrode insulating film. For a memory operation, a high electric field is applied to the control gate electrode and a shift of a threshold voltage generated by injecting electrons from a silicon substrate into the floating gate electrode is used for information storage. At this time, it is desirable that a capacitance of the inter-electrode insulating film is high to maintain a coupling ratio high enough, and also desirable that leak current is small in the inter-electrode insulating film.
A method for manufacturing a memory cell of a general NAND type nonvolatile semiconductor memory device will be described with reference to FIGS. 15A to 19B. FIGS. 15A, 16A, 17A, 18A and 19A and FIGS. 15B, 16B, 17B, 18B and 19B show cross-sections which are orthogonal to each other.
First of all, as shown in FIGS. 15A and 15B, a silicon oxide film 102 with a thickness of approximately 7 nm to 8 nm for a tunneling insulating film is formed by a thermal oxidizing method on a surface of a silicon substrate 101 doped with a desirable impurity. Next, a phosphorus doped polycrystalline silicon layer 103 with a thickness of 60 nm for a floating gate electrode and a mask material 104 for an isolation process are then deposited sequentially by a CVD (chemical vapor deposition) method. Thereafter, the mask material 104, the polycrystalline silicon layer 103 and the tunneling insulating film 102 are sequentially etched by an RIE (reactive ion etching) method using a resist mask (not shown), and furthermore, an exposed region of the silicon substrate 101 is etched to form an isolation trench 106 with a depth of 100 nm.
Next, a silicon oxide film 107 for isolation is deposited on a whole surface and the isolation trench 106 is thus filled completely, and the silicon oxide film 107 in a surface region is then removed by a CMP (chemical mechanical polishing) method to flatten a surface. At this time, the mask material 104 is exposed (FIGS. 16A and 16B).
Subsequently, the exposed mask material 104 is selectively removed, and an exposed surface of the silicon oxide film 107 is then etched with a diluted hydrofluoric acid solution and a sidewall surface 108 of the polycrystalline silicon layer 103 is exposed, and an SiO2/SiN/SiO2 film (hereinafter referred to as an ONO film) 109 having a laminated structure of a silicon oxide film and a silicon nitride film for an inter-electrode insulating film is thereafter deposited over a whole surface. An equivalent SiO2 thickness of the ONO film is approximately 15 nm. At this time, the inter-electrode insulating film 109 is three-dimensionally formed on the surface of the polycrystalline silicon layer 103 and the sidewall surface 108 (FIGS. 17A and 17B). An average dielectric constant of the ONO film is as low as approximately five. For this reason, the three-dimensional inter-electrode insulating film is necessary to increase its effective capacitance by increasing the contacting area with the polysilicon layer 103.
Next, a conductive layer 110 for a control gate electrode made of a polycrystalline silicon layer with a thickness of 100 nm is sequentially deposited by a CVD method, and furthermore, an RIE mask material 111 is deposited by the CVD method. Thereafter, the mask material 111, the conductive layer 110, the inter-electrode insulating film 109, the polycrystalline silicon layer 103 and the tunneling insulating film 102 are sequentially etched by the RIE method using a resist mask (not shown), thereby slit portions 112 are formed in a direction of a word line (FIGS. 18A and 18B). Consequently, the shapes of the polycrystalline silicon layer 103 for a floating gate electrode and the conductive layer 110 for the control gate electrode are determined.
Finally, a silicon oxide film 113 for electrode sidewall is formed on an exposed surface by a thermal oxidation method, and then source and drain regions 114 are formed by using an ion implanting method. Thereafter, an interlayer insulating film 115 is formed by the CVD method in order to cover a whole surface (FIGS. 19A and 19B). Thereafter, a wiring layer is formed by a well-known method to finish a memory cell.
A high electric field is applied to the inter-electrode insulating film 109 in the memory cell of the NAND type nonvolatile semiconductor memory device during writing and erasing operations and leakage current flows therein. The leakage current impedes the charge storage, and charge erasing and writing in the floating gate electrode through the tunneling insulating film. For this reason, it is necessary to suppress the leakage current below a certain reference level which is defined from a device specification. As a result of various investigations, the leakage current level is set to be 1/10 or less of the current flowing to the tunneling insulating film just before completing the writing operation. For example, under the following conditions: a thickness of the tunneling insulating film is 7.5 nm; a coupling ratio of the tunneling insulating film to the inter-electrode insulating film is 0.6; and the inter-electrode insulating film has a three-dimensional structure, an effective electric field applied to the inter-electrode insulating film (which is defined by an “(surface charge density)/(dielectric constant of SiO2)”) is approximately 12 to 18 MV/cm, the leakage current density in the inter-electrode insulating film must be below approximately 1×10−2 A/cm2.
In order to increase the storage capacity of the NAND type nonvolatile semiconductor memory devices, it is necessary to reduce a gate length and a gate width of the memory cells to mount as many cells as possible on individual chips. With a demand for miniaturization of the memory cells, a material with a higher dielectric constant (high-k) has been investigated for the inter-electrode insulating film instead of a conventional ONO film (for example, see JP-A 11-297867 (KOKAI)). The reasons are as follows.
In a generation in which a minimum processing dimension is smaller than 50 nm, distance between the memory cells becomes so small. For this reason, the inter-electrode insulating film, which is formed after forming the sidewall 108 shown in FIGS. 17A and 17B, cannot have three-dimensional structure anymore.
In a miniaturized memory cell, a so-called planar cell structure is required, in which the sidewall is not formed on the floating gate electrode and the inter-electrode insulating film is formed planarly. In the planar cell structure, a material with a higher dielectric constant than the conventional ONO film is required. This is because a use of the material with a high dielectric constant can increase capacitance even if the inter-electrode insulating film is not formed three-dimensionally, but plenary.
Furthermore, an effective electric field applied to the inter-electrode insulating film in the planar cell structure is approximately 30 MV/cm, which is two times higher than that in the three-dimensional cell structure. For the device specification, it is necessary to suppress leakage current density in the inter-electrode insulating film to be equal to or lower than 1×10−2 A/cm2 even at the high electric field region. In the ONO film, however, the leakage current is rapidly increased at a high electric field region. Therefore, it is impossible to use the ONO film as the inter-electrode insulating film of the planar cell. From this viewpoint, it is necessary to use the material with a higher dielectric constant (high-k) for the inter-electrode insulating film, instead of the ONO film. By using the high-k material, it is possible to reduce the leakage current even at the high electric field region by increasing a physical thickness with keeping a low equivalent SiO2 thickness (EOT).
Examples of a promising candidate for the high-k material are rare earth oxide, rare earth nitride or rare earth oxynitride, which includes rare earth elements. These materials generally have high dielectric constants (high-k), and furthermore, have large electron barriers. Therefore, they can be used for the inter-electrode insulating film in the planar cells. However, there are inherent problems of these material system which arise in the fabrication process of a nonvolatile memory cell by the conventional manufacturing method.
As shown in FIGS. 18A and 18B and FIGS. 19A and 19B, after forming the inter-electrode insulating film, it is necessary to perform a thermal treatment for forming a control gate electrode and an electrode sidewall oxide film and a thermal treatment for activating source and drain diffused regions formed by an ion implanting method. For example, a rapid thermal treatment of approximately 30 seconds within a temperature range of 900 to 1000° C. is used for activating the source and drain diffused regions.
FIG. 20 shows changes in an LaAlO3 film structure, in which rare earth oxide of LaAlO3 is deposited on a silicon substrate, by rapid thermal treatment in a nitrogen atmosphere at 900° C. for 30 seconds and 950° C. for 30 seconds. These conditions correspond to thermal treatment for activating the source and drain diffused regions. As shown in a state 201 of FIG. 20, first of all, LaAlO3 in 30 nm with a composition of La:Al=1:1 is deposited on the Si substrate. After rapid thermal treatment at 900° C. for 30 seconds is performed, the film thickness is not changed but crystallization occurs as shown in a state 202. For the composition of La:Al=1:1, an energetically stable perovskite structure is easily formed by the thermal treatment. In the crystallized LaAlO3, current easily flows through grain boundaries. Therefore, an increase in the leakage current is observed. When the thermal treatment at 950° C. (higher temperature) for 30 seconds is performed, it is apparent that an inter-diffusion of Si and La occurs between the silicon substrate and the LaAlO3, and the LaAlO3 is degenerated into La silicate containing Al, and furthermore, a physical thickness rapidly increases (as shown in a state 203 in FIG. 20). This is because oxynitride including a rare earth element such as La has such a property as to be easily taken Si in. The increase in the physical thickness caused by a large amount of Si and La inter-diffusion reduces the dielectric constant. Consequently, capacitance of the inter-electrode insulating film is rapidly reduced resulting in an increase in EOT.
Due to deterioration in the inter-electrode insulating film shown in FIG. 20, a sufficient performance cannot be exhibited in writing, erasing, reading and retaining (storing) operations of amemory cell. Due to crystallization, the leakage current at 12 MV/cm is deteriorated to be equal to or more than 1×10−2 A/cm2. With the reduction in the dielectric constant due to the Si and La inter-diffusion, moreover, an electrical breakdown voltage is dropped, and the leakage current is increased. As the breakdown voltage is dropped to be approximately 20 MV/cm, the leakage current density is equal to or higher than 1×10−2 A/cm2. In both cases, the device specification of the planar cell structure cannot be satisfied.
As shown in FIG. 21, it is also possible to impose barrier layers such as SiN or Al2O3 below the inter-electrode insulating film in order to prevent the inter-diffusion of Si and La (for example, see L. Yan et al., Semicond. Sci. Technol. 19(2004)1-4). However, SiN and Al2O3 have lower dielectric constants than the oxynitride including a rare earth element. For this reason, the effective capacitance of the inter-electrode insulating film may be reduced and an improvement in a performance of a memory cell may become small. In an Al2O3/LaAlO3 interface, where dielectric materials having different dielectric constants contact with each other, fixed charges are easily generated, resulting in a shift of a threshold voltage.
The description has been given to the problem of the crystallization which is caused when rare earth oxide, rare earth nitride or rare earth oxynitride is used for the inter-electrode insulating film or the blocking insulating film, and also the problem of the inter-diffusion of Si, which comes from a conductive material including Si or an insulating material including Si, and a rare earth element. Memory cell characteristics may be improved by solving these problems.
As described above, as the rare earth oxide, the rare earth nitride or the rare earth oxynitride which includes a rare earth element with high dielectric constants is used as the inter-electrode insulating film in the memory cell having the floating gate electrode or the blocking insulating film in the memory cell having the charge storage layer, film quality deteriorates by thermal treatment after deposition of the inter-electrode insulating film or the block insulating film due to crystallization or a reduction in the dielectric constant. From this reason, leakage current characteristics may deteriorate and a sufficient performance cannot be obtained in the writing, erasing, reading, retaining (storing) operations of the memory cells.